It also adds a mixed-signal model capability to IBIS standard by introducing algorithmic modeling components, which allows IBIS-AMI to model complex blocks, such as equalization, DFE and CDR. The new modeling methodology with IBIS-AMI addressed most of the link simulation requirements, such as simulating millions of bits in minutes, crosstalk/jitter analysis and data pattern dependencies. Hspice simulations also have difficulty including crosstalk and jitter impairments. Traditional signal integrity simulation with Hspice-based analysis can’t simulate millions of bits due to slow simulation speeds. SerDes protocols usually require verifying the system to low bit-error-rate (BER) to ensure the system performance. Performing the link simulation is critical to determine if a link meets the design requirements based on the selected transmitter, receiver and backplane in between. Multi-gigabit serial link (SerDes) channels are rapidly becoming the primary mechanism used to transfer high-speed data. In addition, a design example is walked through to provide guidance on high speed serial link design with Altera FPGAs. It first introduces basic knowledge about IBIS-AMI and then compares IBIS-AMI model with transitional Hspice model. This document describes the advantage of IBIS-Algorithmic Modeling Interface (AMI) in high-speed transceiver link simulation.
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